Effect of Clock Duty-Cycle Error on Two-Channel Interleaved Delta Sigma DACs

Time-interleaved ∆Σ (TIDSM) DACs have the potential for a wideband operation. The performance of a twochannel interleaved ∆Σ DAC is very sensitive to the duty-cycle of the half-rate clock. This paper presents a closed-form expression for the SNDR loss of such DACs due to duty cycle error for modulators with a noise transfer function of (1 − z−1). Adding a low-order FIR filter after the modulator helps to mitigate this problem. A closed-form expression for the SNDR loss in the presence of this filter is also developed. These expressions are useful for choosing a suitable modulator and filter order for an interleaved ∆Σ DAC in the early stage of the design process.